The present invention relates to a memory address control apparatus for a data processing (DP) system and, more particularly, to a memory address control apparatus for a plurality of cache memories.
Recent improvements in packaging technology and IC (integrated circuit) and LSI (large-scale integration) technology has improved the processing speed of computers. This results in a large gap between the operation speed of a central processing unit (CPU) and the access speed for a main memory unit (MMU) having a large capacity. To reduce such a speed gap there is proposed a DP system equipped with a high speed buffer memory (or cache memory) having a small capacity for storing a copy of part of the main memory. For details of the proposed DP system, reference may be made to an article by J. S. Liptay, entitled "Structural aspects of the System/360 Model 85 II, the cache", IBM System Journal, Vol. 7, No. 1, pp. 15-21, 1968. To improve the processing speed of such a system, it is necessary to improve the MMU-access time and to enlarge the memory capacity of the cache memory (CM). For this purpose, an improved DP system is proposed in U.S. Pat. No. 3,618,041. The proposed system is equipped with two CMs for the data and instruction words. The processing speed of the whole system cannot be improved with this system, because attention is not paid to the capacity ratio of the two CMs used, even if the probability that the desired data is not stored in either CM (referred to hereunder as "missing probability") is maintained at a similar degree to that in the other DP system using one CM.
Also, another DP system using a virtual memory technique is disclosed in U.S. Pat. No. 3,317,898. For the efficient use of the MMU, this system has a directory memory for translating a logical address for the MMU into a corresponding real address for the MMU to dynamically relocate various programs on the MMU and thereby to use the MMU as a virtual memory having a memory capacity larger than the physical capacity of the MMU (see the U.S. Pat. No. 3,761,881 for details of such translating operation). For this DP system, the adoption of two CMs can be similarly considered. However, the system thus achieved has the same disadvantages for the same reasons as those stated above.